In the semiconductor photolithography process, the bake cycles are extremely important for uniformity and repeatability of the various process steps, with the most significant being the post exposure bake (PEB) cycle in a chemically amplified resist process. In this process, a photoresist is applied to the semiconductor surface. The photoresist is subjected to a mask exposure to apply a circuit pattern. Chemically amplified resists require both an exposure dose to generate a latent acid image, and a thermal dose to drive the deblocking reaction that changes the solubility of the resist. The post exposure bake must optimize the balance between relative rates of the diffusion and reaction processes.
Hot plates having uniformities within a range of a few tenths of a degree centigrade are currently available and are generally adequate for current process methods. However, there is an uncontrolled phenomena in the production implementation of this PEB process that is likely to cause severe issues as feature sizes continue to decrease. The phenomena, or problem, is that the hot plates are precisely calibrated using a flat bare silicon wafer with imbedded thermal sensors. But actual production wafers with deposited films on the surface of the silicon exhibit small amounts of warpage due to the stresses induced by the deposited films. This warpage can cause the normal gap between the wafer and the hot plate (referred to as the proximity gap), to vary across the wafer from a normal value of approximately 100 μm by as much as 100 μm deviation from the mean proximity gap.
This variability in the proximity gap changes the heat transfer characteristics in the area of the varying gap causing temperature non-uniformity on the wafer surface. This temperature difference can result in a change in critical dimension (CD) in that area of several nanometers, which can approach the entire CD variation budget for current leading edge devices, and will exceed the projected CD budget for smaller devices planned for production in the next few years.
In one current hot plate system, a combined cool plate and baking plate reside in one module. In this module, the silicon wafer is placed on the cool plate and then transferred internally in the module to the bake plate, and then, after baking, returned to the cool plate where it is subsequently removed to continue processing. The bake plate contains multiple zone heating elements for precise calibration of bake temperatures. For advanced work, proposals have been published to address the warpage issue by relying on a hope for consistency of warpage by device layer, and zone-based bake temperature adjustment for all waters of a certain device layer.